The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a recess gate.
As semiconductor devices become more highly integrated, gate channel length increases and ion implant doping concentration decreases. A typical method for forming a gate over a planar active region, that is, a planar gate line formation method, causes electric field to increase. Thus, it is difficult to secure refresh characteristics of the device because of junction leakage caused by the electric field increase.
To secure the refresh characteristics of the semiconductor device, a method for forming a three-dimensional (3D) gate structured recess gate for recessing a region below gate patterns is proposed to increase the channel length.
FIGS. 1A to 1C are cross-sectional views describing a typical method for fabricating a semiconductor device with a recess gate.
Referring to FIG. 1A, an isolation layer 12 is formed over a substrate 11 to define an active region. The isolation layer 12 and the active region are selectively etched to form recess patterns 13.
Referring to FIG. 1B, gate patterns 14 protruding from the substrate 11 are formed to fill the recess patterns 13. The gate patterns 14 may include a stack structure of a first electrode 14A, a second electrode 14B, and a gate hard mask 14C. Herein, a linewidth of the recess patterns 13 in the isolation layer 12 can be increased through a cleaning process performed before the gate patterns 14 are formed.
An etch barrier layer 15 is formed over a resultant structure including the gate patterns 14. An insulation layer 16 is formed to fill the gap between the gate patterns 14.
Referring to FIG. 1C, the insulation layer 16 and the etch barrier layer 15 between the gate patterns 14 are etched to open the substrate 11. A conductive material is filled in the resulting spaces to form a landing plug contact 17.
As described above, in the typical process, the recess patterns 13 and the landing plug contact 17 are formed to improve the refresh characteristics.
According to the typical method, however, an isolation layer 12 can be damaged by the cleaning process performed before the substrate 11 is open and filled with the conductive material. Thus, a short 100 can occur between the gate patterns 14 and the landing plug contact 17.